Course Description

Course Name

VLSI Design and Laboratory

Session: VSOS3221

Hours & Credits

3 Credits

Prerequisites & Language Level

Taught In English

  • There is no language prerequisite for courses at this language level.


Understanding of Semi-custom design flow of VLSI design

Course Objectives
To get familiar with verilog Language and Synthesis Process for VLSI design

Verilog HDL : "A Guide to Digital Design and Synthesis", Samir Palnitakar 2nd Edition, Plantice Hall


Hierarchical Modeling Concepts

Basic Concepts " verilog syntax conventions

Modules and Prots, Gate-level modeling

Gate-level Modeling

Behavioral Modeling

Behavioral Modeling

Fixed Points arithmetic & Testbench

Tasks and Funcitons

Loop statesments

Testbench and Fixed point models

FIR filter design

IIR filter design

Folded Architecture

Project 2 Presentation

*Course content subject to change